NT4GT72U4ND0BV-3C Nanya 4GB PC2-5300 DDR2-667MHZ ECC Registered CL5 240-Pin

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NT4GT72U4ND0BV-3C Nanya 4GB PC2-5300 DDR2-667MHZ ECC Registered CL5 240-Pin DIMM Dual Rank

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Specifications   
Memory Category DRAM Chip
Density 38654706 kbits
Number of Words 512000 k
Bits per Word   72 bits
Package Type    ROHS COMPLIANT, DIMM-240
Pins    240
Supply Voltage  1.55
Access Time     0.4500 ns

 
Features, Applications

Features

1GB 128Mx72 and 256Mx72 DDR2 Fully Buffered DIMM based 128Mx8 DDR2 SDRAM 512Mx72 DDR2 Fully Buffered DIMM based 256Mx4 DDR2 SDRAM (NT5TB256M4DE-3C) JEDEC Standard 240-pin Fully Buffered ECC Dual In-Line Memory Module. Performance: Speed Sort DIMM Latency* f DQ Clock Frequency Clock Cycle DQ Burst Frequency PC2-5300 -3C MHz ns Mbps Unit Intended for 333MHz applications. Inputs and outputs are SSTL-18 compatible. VDD ± 0.075V, VDDQ ± 0.075V Host Interface and AMB component industry standard compliant. Support SMBus protocol interface for access to the AMB configuration registers. Detects errors on the channel and reports them to the host memory controller. Automatic DDR2 DRAM Bus Calibration. Full Host Control of the DDR2 DRAMs. Over-Temperature Detection and Alert. MBIST & IBIST Test Functions. Transparent Mode for DRAM Test Support. Serial Presence Detect (SPD) Gold contacts RoHS Compliant products SDRAMs in 60-ball BGA Package
Description

Fully Buffered 240-Pin Double Data Rate 2 (DDR2) Synchronous DRAM Dual In-Line Memory Module (DIMM), organized as an eight bank 512Mx72 (4GB) high-speed memory array. The module uses nine 128Mx8 (1GB), eighteen (2GB), or thirty-six (4GB) DDR2 SDRAMs in BGA packages. These DIMMs are manufactured using raw cards developed for broad industry use as reference designs. The use of these common design files minimizes electrical variation between suppliers. All NANYA DDR2 SDRAM DIMMs provide a high-performance, flexible 8-byte interface a 5.25" long space-saving footprint. The DIMM is intended for use in applications operating to 333MHz clock speeds and achieves high-speed data transfer rates to 667 Mbps. Prior to any access operation, the device latency and burst type/length/operation type must be programmed into the DIMM by address inputs A0-A13 and I/O inputs BA0, BA1, and BA2 using the mode register set cycle.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.